The present invention relates to a decoder circuit used in a semiconductor memory device.
FIG. 17 is a circuit diagram showing a structure of a part of a decoder circuit as a first conventional circuit or the like which is used in a semiconductor memory device used as a versatile memory product.
As shown in the drawing, the first conventional circuit is comprised of a high-voltage circuit portion 21 and a low-voltage circuit portion 25. The low-voltage circuit portion 25 performs a low-voltage operation using a low power supply voltage VD of about 1.5 V and a GND voltage VS of about 0 V as a “H” level and a “L” level, respectively. The high-voltage circuit portion 21 performs a high-voltage operation using a high power supply voltage VP of about 5 to 10 V and a negative-side power supply voltage VN of 0 V to a negative high voltage level as the “H” level and the “L” level, respectively.
The low-voltage circuit portion 25 is comprised of a 3-input NAND gate G21, receives input signals IN22 to IN24, and outputs the output signal thereof to the high-voltage circuit portion 21. An input signal IN21 is directly outputted to the high-voltage circuit portion 21 without any alteration.
The high-voltage circuit portion 21 is comprised of a load current generating portion 31, an NMOS transistor QN31, and an inverter G22. In the NMOS transistor QN31, one electrode receives the output of the NAND gate G21, the other electrode is coupled to a node N31, and a gate electrode receives the input signal IN21.
The load current generating portion 31 is comprised of a PMOS transistor QP31. In the PMOS transistor QP31, one electrode receives the high power supply voltage VP, a gate electrode receives a (load current) control signal SC21, and the other electrode is coupled to the node N31, i.e., the other electrode of the NMOS transistor QN31. Because the control signal SC21 is constantly fixed to the “L” level (negative-side power supply voltage VN), the PMOS transistor QP31 is in a normally-ON state so that the high power supply voltage VP is constantly imparted to the node N31.
However, the first conventional circuit according to the first embodiment is designed to satisfy a first operation condition under which, when the output of the NAND gate G21 is on the “L” level (GND voltage VS), the (“L”-level) driving forces of the NAND gate G21 and the NMOS transistor QN31 exceed the driving force of the PMOS transistor QP31 to forcibly set the node N31 to the GND voltage VS. For example, by setting the gate width of each of MOS transistors (particularly the MOS transistor for setting the GND voltage VS) configuring the NAND gate G21 and the NMOS transistor QN31 to a value larger than that of the PMOS transistor QP31 or the like, a structure which satisfies the foregoing first operation condition is implemented.
The inverter G22 is implemented by a CMOS structure comprised of a PMOS transistor QP32 and an NMOS transistor QN32 which are coupled in series to share a gate electrode. That is, the one electrode of the PMOS transistor QP32 receives the high power supply voltage VP, the one electrode of the NMOS transistor QN32 receives the negative-side power supply voltage VN, and the shared gate electrode of both off the PMOS transistor QP32 and the NMOS transistor QN32 is coupled to the node N31. A signal obtained from the other electrode of the PMOS transistor QP31 (NMOS transistor QN31) is outputted as an output signal OUT21. The output signal OUT21 drives a word line or the like.
FIG. 18 is a waveform diagram showing an operation of the first conventional circuit. Referring to the drawing, a decoding operation of the first conventional circuit will be described hereinbelow.
During a non-selected state, at least one of the input signals IN21 to IN24 which are predecode signals is on the “L” level, and the output of the NAND gate G21 is on the “H” level, or the NMOS transistor QN31 is in an OFF state so that there is no extraction of the potential of the node N31 to the “L” level. Accordingly, the potential of the node N31 is set to the high power supply voltage VP by a charging operation by the PMOS transistor QP31 in the normally-ON state.
As a result, the “L” level (negative-side power supply voltage VN) is outputted as the output signal OUT21 from the inverter G22 to bring the word line which receives the output signal OUT21 or the like into the non-selected state.
On the other hand, during a selected state, the input signals IN21 to IN24 are all on the “H” level, the output of the NAND gate G21 is set to the “L” level, and the NMOS transistor QN31 is in the ON state to satisfy the foregoing first operation condition. Accordingly, the potential of the node N31 is extracted to the “L” level (GND voltage VS).
As a result, the “H” level (high power supply voltage VP) is outputted as the output signal OUT21 from the inverter G22 to bring the word line which receives the output signal OUT21 or the like into the selected state.
Since the first conventional circuit thus structured performs the decoding operation while setting the PMOS transistor QP31 configuring the load current generating portion 31 to the normally-ON state, it follows that a through current is constantly generated between the high power supply voltage VP and the GND voltage VS in the selected state.
FIG. 19 is a circuit diagram showing a structure of a part of a decoder circuit as a second conventional circuit which is used in a semiconductor memory device used as a versatile memory product or the like. As for the same parts as those of the first conventional circuit shown in FIG. 17, the description thereof will be omitted appropriately by providing the same reference numerals.
As shown in the drawing, the second conventional circuit is comprised of a high-voltage circuit portion 22 and a low-voltage circuit portion 26. The low-voltage circuit portion 26 performs the same low-voltage operation as performed by the low-voltage circuit portion 25. The high-voltage circuit portion 22 performs the same high-voltage operation as performed by the high-voltage circuit portion 21.
The low-voltage circuit portion 26 is comprised of a 3-input NAND gate G23, receives input signals IN22 to IN24, and outputs the output signal thereof to the high-voltage circuit portion 22. An input signal IN21 is directly outputted to the high-voltage circuit portion 22 without any alteration.
The high-voltage circuit portion 22 is comprised of a load current generating portion 32, an NMOS transistor QN33, an inverter G22, and a PMOS transistor QP34. In the NMOS transistor QN33, one electrode receives the output of the NAND gate G23, the other electrode is coupled to a node N32, and a gate electrode receives the input IN21.
The load current generating portion 32 is comprised of a PMOS transistor QP33. In the PMOS transistor QP33, one electrode receives the high power supply voltage VP, a gate electrode receives a control signal SC22, and the other electrode is coupled to the node N32. The control signal SC22 is set to the “L” level (negative-side power supply voltage VN) only during a predetermined initial period after the initiation of each decoding operation, while it is set to the “H” level (high power supply voltage VP) during the other period.
The inverter G22 uses the node N32 as an input portion, and outputs an output signal OUT22 obtained by inverting a signal obtained from the node N32 from a node N33 as the other electrode of the PMOS transistor QP32 (NMOS transistor QN32).
In the PMOS transistor QP34, one electrode receives the high power supply voltage VP, a gate electrode is coupled to the node N33, and the other electrode is coupled to the node N32.
FIG. 20 is a waveform diagram showing an operation of the second conventional circuit. Referring to the drawing, a decoding operation of the second conventional circuit will be described hereinbelow.
In the second conventional circuit, the control signal SC22 is on the “L” level during the initial predetermined period after the initiation of each decoding operation, and the pre-process of charging the node N32 to the high power supply voltage VP is inevitably executed by the PMOS transistor QP33 which is in the ON state during this period.
During the non-selected state, after the pre-process mentioned above, at least one of the input signals IN21 to IN24 which are pre-decode signals becomes “L”, and the output of the NAND gate G23 becomes “H”, or the NMOS transistor QN33 is brought into the OFF state. Accordingly, the potential of the node N32 is not extracted to the “L” level, and is set to the high power supply voltage VP by a charging operation by the PMOS transistor QP33 in the pre-process.
As a result, the “L” level (negative-side power supply voltage VN) is outputted as the output signal OUT22 by the inverter G22 to bring the word line or the like which receives the output signal OUT22 into the non-selected state.
After the control signal SC22 has risen to the “H” level, the PMOS transistor QP33 is brought into the OFF state. However, the output signal OUT22 on the “L” level is imparted to the gate electrode of the PMOS transistor QP34 to allow the PMOS transistor QP34 in the ON state to keep the potential of the node N32 at the high power supply voltage VP. Therefore, even after the rise of the control signal SC22 to the “H” level, the output signal OUT22 retains the “L” level so that the non-selected state is maintained.
Thus, as a result of bringing the PMOS transistor QP34 which receives the output signal OUT22 of the inverter G22 at the gate electrode thereof into the ON state, the “L” level of the output signal OUT22 can be latched so that, even after the OFF state of the PMOS transistor QP3, the non-selected state is maintained.
On the other hand, during the selected state, after the pre-process mentioned above, all of the input signals IN21 to IN24 become “H”, the output of the NAND gate G23 becomes “L”, and the NMOS transistor QN33 is brought into the ON state so that the potential of the node N32 is extracted to the “L” level (GND voltage VS).
As a result, the “H” level (high power supply voltage VP) is outputted as the output signal OUT22 from the inverter G22 to bring the word line which receives the output signal OUT22 or the like into the selected state.
After the rise of the control signal SC22 to the “H” level, the output signal OUT22 on the “H” level is imparted to the gate electrode of the PMOS transistor QP34 to turn OFF the PMOS transistor QP34. As a result, the PMOS transistors QP33 and QP34 each for charging the node N32 to the high power supply voltage VP are both turned OFF. Therefore, there is no flow of a through current between the high power supply voltage VP and the negative-side power supply voltage VN during the selected state.
Thus, the PMOS transistor QP34 functions as a half latch which latches only the output signal OUT22 on the “L” level.
The second conventional circuit thus structured performs the decoding operation after keeping the PMOS transistor QP32 configuring the load current generating portion 32 in the ON state only for a predetermined period during the foregoing pre-process for the decoding operation. Therefore, unlike in the first conventional circuit, there is no occurrence of a through current to achieve lower power consumption. The second conventional circuit is disclosed in, e.g., Patent Document 1.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2001-101881